Continuing advances in semiconductor technology have made feasible higher levels of integration and higher clock frequencies. As a result, existing computer integrated devices are increasingly being incorporated into larger, faster, and more diverse semiconductor chips such as peripheral hardware controllers. This allows a single chip to perform many different functions inclusively. One of many challenges in the integration of existing integrated devices into faster semiconductor chips is clock frequency compatibility. For numerous reasons including the limitation of the technology available at the time the existing integrated device was designed, an integrated device is more likely to operate at a slower clock frequency than the multi-functional chip incorporating such device.
The National Semiconductor PC87311 SuperI/O.TM. is an example of a larger, faster, and more diverse chip which incorporates an existing integrated device with different operating clock frequency, namely the National Semiconductor PC16C550 UART, in its architecture. The PC87311 is a multi-functional controller (i.e., disk and serial communication controller) with an operating clock frequency of 24 MHz. On the other hand, the PC16C550 UART is an asynchronous serial communications integrated device with an operating clock frequency of 1.8432 MHz. The PC16C550 UART includes a baudrate generator to generate one of many programmed serial baudrates. The baudrate generator utilizes driver software to program different baudrate values which are based on an allowable range of the operating clock frequency received from the PC16C550 UART.
To make the PC16C550 UART compatible with the PC87311, the PC87311 clock frequency is scaled down by a factor of 13 to produce a 1.84615 MHz output scaled clock frequency that is within 0.16% of the 1.8432 MHz operating clock frequency of the PC16C550 UART. As faster clock frequencies in higher integration semiconductor chips become available, however, greater flexibility in clock rate adjustment is needed to accommodate existing integrated devices such as the PC16C550 UART. More particularly, fractional clock rate adjustment is crucial in fine-tuning the output scaled clock frequency to within the allowable range of clock frequency of the existing integrated device.
The binary rate multiplier circuit (BRM) such as the Texas Instruments SN5497 and the SN7497 is used in digital-to-analog and analog-to-digital conversions. In the field of industrial process measurement, the BRM circuit has been used in measuring systems that have nonlinear sensors such as thermocouples. The BRM circuit modulates digital waveform input signals representing temperature measurements to approximate the nonlinear output characteristics of the thermocouples. Reference is now made to FIG. 1 which illustrates an overview of an industrial process measurement system 100 which incorporates an BRM for the purpose stated above.
Analog voltage signal 101 generated from the thermocouple is provided as input to analog-to-digital (A/D) converter 102 which converts analog signal 101 to digital clock signal 103. To perform this conversion, A/D converter 102 implements an integrated dual slope conversion scheme in which analog signal 101 is integrated over a designated time period. Next, the value of the integrated signal achieved following the designated time period is used as a starting point for integrating a reference signal until the integrated reference signal drops down to zero. The time required for the integrated reference signal to drop to zero is measured in terms of clock pulses which are then provided as digital waveform signal 103 to BRM circuit 104. In short, digital waveform signal 103 corresponds to the thermocouple's calibrated temperature measurement.
BRM circuit 104 modulates digital waveform signal 103 to conform to the thermocouple's voltage vs. temperature conversion curve over a desired operating temperature range. To conform digital waveform signal 103 to the known voltage vs. temperature curve, waveform 104 is scaled by known divisor values. FIG. 2 shows BRM circuit 104 used in industrial process measurement system 100. The BRM circuit 104 includes fixed period binary counter 201, programmable divisor register 202, and BRM logic 203 which couples divisor register 202 to period counter 201. BRM circuit 104 produces as its output scaled digital waveform signal 105.
Referring back to FIG. 1, scaled digital waveform signal 105 is provided as input to Fahrenheit-Celsius converter 106 to convert from waveform counts to temperature reading in either Fahrenheit or Celsius. Temperature reading 107 is then sent to display counter 108 for display purposes.
The limitation with the BRM that was used in industrial process measurement system 100 is that it has only one degree of freedom through the programmable divisor register. In other words, the BRM that was used in industrial process measurement system 100 has only one variable, the divisor register 202, for adjustment. This severely limits the amount of fine-tuning needed in scaling clock frequencies. It therefore makes the applicability of the BRM circuit to semiconductor chips incorporating computer integrated devices problematic.